ÄÜÅÙÃ÷ »ó¼¼º¸±â
Digital Clamp Circuit Design with Python and Verilog


Digital Clamp Circuit Design with Python and Verilog

Digital Clamp Circuit Design with Python and Verilog

<¿ÕÀ±¼º> Àú | À¯ÆäÀÌÆÛ(°³ÀÎÃâÆÇ)

Ãâ°£ÀÏ
2013-12-24
ÆÄÀÏÆ÷¸Ë
ePub
¿ë·®
3 M
Áö¿ø±â±â
PC½º¸¶Æ®ÆùÅÂºí¸´PC
ÇöȲ
½Åû °Ç¼ö : 0 °Ç
°£·« ½Åû ¸Þ¼¼Áö
ÄÜÅÙÃ÷ ¼Ò°³
¸ñÂ÷
ÇÑÁÙ¼­Æò

ÄÜÅÙÃ÷ ¼Ò°³

ÀÌ Ã¥Àº Clamp ȸ·Î¸¦ Digital ·Î ±¸ÇöÇÏ´Â ¹æ¹ýÀ» ¼Ò°³ÇØ ³õÀº Ã¥ÀÌ´Ù. Çϵå¿þ¾î·Î ¼³°èÇϱâ Àü¿¡ Python ¾ð¾î·Î ¸ðµ¨¸µÇÏ°í ½Ã¹Ä·¹À̼ÇÇØ º¼ ¼ö ÀÖ°Ô ±¸¼ºµÇ¾î ÀÖ°í ¶ÇÇÑ Verilog ·Î ¼³°èµÈ Çϵå¿þ¾î¿¡ ´ëÇؼ­µµ ½Ã¹Ä·¹À̼ÇÀ» ÇØ º¸°í ±× °á°ú¸¦ Python À¸·Î ¸ðµ¨¸µÇÑ °Í°ú ºñ±³ÇØ º¼ ¼ö ÀÖµµ·Ï ÇÏ¿´´Ù. ÀüÀÚ°øÇÐÀ» Àü°øÇÏ¿© IC ¼³°è¿¡ °ü½É °®°í ÀÖ´Â Çлýµé¿¡°Ô ¼³°è ½Ç¹« °¨°¢À» ÁõÁø½ÃÅ°´Âµ¥ µµ¿òÀÌ µÉ °ÍÀÌ´Ù.

¸ñÂ÷

Chapter 01
Chapter 02
ÆDZÇÆäÀÌÁö
1. ¼³°è ȯ°æ ±¸ÃàÇϱâ
2. Python À¸·Î Digital Clamp Circuit ¼³°èÇϱâ
2.2 DCC Modeling & Simulation with Python
2.3 Input Stimulus File Á¦ÀÛ
3. Verilog ·Î Digital Clamp Circuit ¼³°èÇϱâ
3.2 Verilog ·Î ±¸ÇöÇϱâ
3.3 Testbench & Simulation
3.4 Python Modeling °ú Verilog ºñ±³